The invention relates to improved EEPROM devices and methods of making same and, more particularly, the invention relates to an EEPROM with reduced area. Still more particularly, the present invention relates to a reduced area EEPROM device with dielectric coupling capacitance between poly lines.
An Electrically Erasable Programmable Read Only Memory (EEPROM) is a memory cell capable of storing a bit of information, which can be programmed and erased, enabling the EEPROM cell to be reused. EEPROMs are commonly used in either single cells or an array of memory cells, such as flash EEPROMs, which can be erased all at once. Erasure is accomplished by application of an electrical field.
EEPROM memory cells use floating gate transistor technology. A floating gate transistor has a source region and a drain region operably connected with a floating gate. A floating gate is a gate designed to receive an electrical charge making use of a quantum physics effect known as tunneling. The presence or absence of an electrical charge at the floating gate determines the bit value (1 or zero) of the EEPROM memory cell. An EEPROM with a charge above a predetermined threshold represents a xe2x80x9c1,xe2x80x9d which represents an erased cell. A programmed EEPROM bit or a xe2x80x9c0xe2x80x9d is represented by an empty cell having no significant charge.
Programming, or writing data to an EEPROM, involves applying a specified programming voltage for a specified length of time. Reading the EEPROM cell involves applying a particular voltage and using cell sensor circuitry to detect current movement from the drain to the source via the floating gate. In order to erase the EEPROM cell, the charge stored on the floating gate must be returned to the substrate of the device. This erasure process is accomplished by the application of an electric field sufficient to drive the extra floating gate electrons back to the substrate.
Several problems arise in the art associated with erasure of EEPROMs. One type of EEPROM known in the art is the double-poly EEPROM. As shown in FIG. 1, the prior art double-poly EEPROM has two polysilicon layers. A floating gate layer is separated from a control gate layer by a high quality dielectric material, such as an oxide material. The control gate is used for causing electrons to be pushed through the thin oxide layer separating the control gate from the floating gate so that a cell sensor can read the EEPROM memory cell. The application of a higher voltage charge at the control gate erases the cell by raising the turn flow above a specified threshold. Problems with double-poly EEPROM cells arise from the structure which requires application of two separate polysilicon layers and an intervening oxide layer. In semiconductor manufacturing, the number of layers is directly related to the cost of manufacturing. Additional layers require additional manufacturing steps, and additional manufacturing steps, in turn, mean increased cycle time and increased potential for defects, leading to lower yields.
Attempts to address the above-mentioned and other problems in manufacturing EEPROM devices include the use of a single polysilicon layer EEPROM device. Such efforts provide an n-well as a control gate and erase region. However, high voltages required for programming an erasure require that the n-well portion of the device be relatively large. This makes the overall single-poly EEPROM cells large by semiconductor standards. For example, sizes can range from 200 um2 to 500 um2 per cell which limits their application to designs requiring only a few tens of cells per die.
EEPROM technology would be significantly benefitted by EEPROM cells manufactured with the advantages of using a single polysilicon layer if the overall area of the EEPROM cell structure could be reduced. Such improvements would lead to significant advantages including, but not limited to, reductions in costs, cycle times, defects and the capability to include more memory cells within a given area on a die.
The present invention provides a decreased area EEPROM device with a single polysilicon layer. The invention also provides a method of making a reduced area EEPROM device.
According to one embodiment, discloses is an Electrically Erasable Programmable Read Only Memory (EEPROM) device. The device comprises a source region, a drain region and a polysilicon layer. The polysilicon layer further comprises a floating gate comprising at least one polysilicon finger operatively coupling the source region and drain region and a control gate comprising at least one polysilicon finger capacitively coupled to the floating gate.
According to another embodiment, an EEPROM device comprising a source region, a drain region and a polysilicon layer is disclosed. The polysilicon layer further comprises a floating gate comprising at least one polysilicon finger operatively coupling the source region and drain region and a control gate comprising at least one polysilicon finger capacitively coupled to the floating gate. A field oxide layer underlying the polysilicon layer.
Further disclosed is a method of making an EEPROM device. The method comprises the steps of forming a source region and a drain region and forming a floating gate operatively coupling the source region with the drain region. Next, a control gate is capacitively coupled to the floating gate wherein the floating gate and control gate are configured to provide capacitance sufficient for controlling the floating gate for writing and erasing the device.
A technical advantages provided by the invention is a decrease in EEPROM cell area compared to prior art EEPROM devices using an n-well control gate.
Another advantage of the invention is reduced die cost as a result of the reduced device area.